Department of Computer Science and Technology, West Cambridge
Fixed-term: The funds for this post are available until 30 September 2027.
Applications are invited for a full-time Research Assistant/Associate to work on the design and implementation of next-generation AI hardware (ASIC) accelerators.
The UK's Advanced Research Invention Agency (ARIA) is supporting an ambitious programme of work that aims to reduce the the cost of AI by more than 1000x: https://www.aria.org.uk/opportunity-spaces/nature-computes-better/scaling-compute/
The objective of our project, funded within this programme, is to develop a scalable and modular simulation framework. At the lowest level, this will involve the design and characterisation of a novel configurable hardware LLM accelerator. The successful candidate will be able to lead the continued design and implementation of this accelerator, i.e. exploring optimisations at the architectural and microarchitectural levels and pushing the design through the ASIC / EDA tools to generate accurate estimates of performance, power and area (PPA) for inclusion in our simulator framework. Candidates will ideally have worked on complex digital hardware designs and be familiar with standard EDA design tools from Cadence and Synopsys. Familiarity with standard design verification (DV) procedures and continuous integration (CI) setups would be beneficial. Knowledge of machine learning workloads and the design of machine-learning accelerators would be advantageous. Experience focused on novel semiconductor devices or training ML models is not particularly relevant for this role. It should be possible to take someone with extensive experience of using FPGA tools and provide them the necessary training to use the ASIC tools.